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<h3 class="section" id="x86_002dSpecific-Memory-Model-Extensions-for-Transactional-Memory"><span>6.57 x86-Specific Memory Model Extensions for Transactional Memory<a class="copiable-link" href="#x86_002dSpecific-Memory-Model-Extensions-for-Transactional-Memory"> &para;</a></span></h3>

<p>The x86 architecture supports additional memory ordering flags
to mark critical sections for hardware lock elision. 
These must be specified in addition to an existing memory order to
atomic intrinsics.
</p>
<dl class="table">
<dt><code class="code">__ATOMIC_HLE_ACQUIRE</code></dt>
<dd><p>Start lock elision on a lock variable.
Memory order must be <code class="code">__ATOMIC_ACQUIRE</code> or stronger.
</p></dd>
<dt><code class="code">__ATOMIC_HLE_RELEASE</code></dt>
<dd><p>End lock elision on a lock variable.
Memory order must be <code class="code">__ATOMIC_RELEASE</code> or stronger.
</p></dd>
</dl>

<p>When a lock acquire fails, it is required for good performance to abort
the transaction quickly. This can be done with a <code class="code">_mm_pause</code>.
</p>
<div class="example smallexample">
<pre class="example-preformatted">#include &lt;immintrin.h&gt; // For _mm_pause

int lockvar;

/* Acquire lock with lock elision */
while (__atomic_exchange_n(&amp;lockvar, 1, __ATOMIC_ACQUIRE|__ATOMIC_HLE_ACQUIRE))
    _mm_pause(); /* Abort failed transaction */
...
/* Free lock with lock elision */
__atomic_store_n(&amp;lockvar, 0, __ATOMIC_RELEASE|__ATOMIC_HLE_RELEASE);
</pre></div>

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